Semiconductor integrated circuit design can be thought of as a collaboration between circuit schematic designers and physical designers.
Initially, a system level designer creates a functional specification of what a user wants the integrated circuit (hereinafter also referred to as IC or chip) to do. Various known computer-implemented tools and languages, such as MATLAB, Sinulink, Verilog systems, can be used to generate the functional specification. A Register Transfer Level (RTL) design is then produced, which describes operation of circuitry on the chip, and interconnections to chip inputs and outputs. The RTL design specifies flow of signals or transfer of data between circuit elements, for example logic gates or hardware registers, and further specifies logical operations performed on such signals.
A circuit schematic designer designs the functionality of a circuit, using schematic representations of circuit components and modules. The circuit schematic designer also designs interconnections between the circuit components and modules, where the interconnections are in form of a topology. The topology is abstract, meaning that a given interconnection between two components does not show relative positions of the components, or distance of an interconnection path between the components, but merely that there is an interconnection between the components. The schematic design can be in the form of a netlist, which represents the components and the modules, with respective input and output contact points, and the interconnections between contact points of various components and modules. Thus, a data flow can be deduced, at a schematic level, for the components, the modules, and the interconnections in the schematic design.
A physical designer prepares a layout for the IC, with circuit topology the chip would have. In a physical design, the components and the modules are positioned relative to each other, and shape, size, length, of interconnections between the components and the modules are specified. The physical designer takes the RTL design, and a library of available circuit components, for example logic gates, and creates a physical chip design. This involves figuring out which gates to use, defining locations for the gates, and wiring the gates together. The physical design is sometimes referred to as a floorplan for the integrated circuit. The physical design step does not affect functionality of the integrated circuit, but does substantially influence circuit operating parameters, for example operation speed of the chip operates, and what will be the cost of fabrication of the chip.
Physical designers typically collaborate with RTL designers to produce a floorplan which optimizes data flow through chip components and modules, and from the chip inputs to the chip outputs. For instance, the physical designers might manually trace and draw net connectivity and data flow pathways, and then consult RTL designers to verify correctness of the data flow. Due to the large size of many IC design netlists, and to the difficulty and complexity of macro editing tasks used in physical design process, analysis of design netlist data flow is time-consuming, and often requires multiple collaborative iterations between the physical and RTL designers. Hence, efficiency of the physical design process is desirable.